The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices including thyristor-based devices.
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner, as well as forming the devices in a variety of arrangements, and in particular for highly-dense applications, has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F2 and 8 F2, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors, or 6 transistors, which result in much lower density, with typical cell size being between about 60 F2 and 150 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in providing a bi-stable element for such memory cells and in overcoming many previously unresolved problems for thyristor-based memory applications. This type of NDR device has a control port that is capacitively coupled to a relatively-thin thyristor body. The thyristor body is sufficiently thin to permit modulation of the potential of the thyristor body in response to selected signals capacitively coupled thereto via the control port. Such capacitively-coupled signals are used to enhance switching of the thyristor-based device between current-blocking and current-conducting states. However, an important consideration in semiconductor device design, including the design of memory cells employing thin capacitively-coupled thyristors, is forming devices in highly-dense arrays to meet demands for ever-increasing memory volume and speed.
One method to make a thyristor-based NDR device is to form a vertical silicon pillar by first depositing a layer of silicon on a substrate and then subsequently masking and etching the deposited silicon layer, leaving the pillar behind. However this method presents a number of manufacturing issues, including those related to the forming of other structures in and on the substrate, such as planar MOSFET devices, after the thyristor pillar is formed. For example, it is extremely difficult to add STI (Shallow Trench Isolation) after the pillar etch since STI usually requires a chemical-mechanical polishing (CMP) step. Also, patterning used to form a mask, such as for photolithography, is difficult near such a pillar due to resist puddling. Additionally, angled implants used after the formation of the pillar may introduce shadowing problems, resulting in the pillar being implanted instead of the intended implantation of other devices near the thyristor. Implanting the pillar to form the thyristor, as well as masking horizontal devices near the pillar, such as source/drain regions of a MOSFET, is also challenging.
The above-mentioned and other difficulties associated with the formation of vertical thyristor-based devices have and continue to present challenges to the manufacture and implementation of such devices.
The present invention is directed to a thyristor-based memory cell that addresses the above-mentioned challenges. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor device is manufactured having a thyristor structure that addresses the challenges mentioned hereinabove. The device includes a transistor coupled in series with a thyristor, with the transistor having a gate over the upper surface and source/drain regions in the substrate below the upper surface. A portion of the thyristor extends over the upper surface with one of the source/drain regions also forming an emitter of the thyristor. With this approach, the semiconductor device can be formed in a relatively compact arrangement, which is particularly useful in high-density memory applications. Furthermore, the thyristor can be formed after transistors and/or other circuit elements of the device have been formed, which makes this approach relatively efficient to manufacture.
In a more particular example embodiment of the present invention, a vertically-arranged thin capacitively-coupled thyristor device is formed over a surface of a semiconductor substrate having a source/drain region of a transistor formed therein, and a gate for the transistor formed on the surface. First, an oxide is formed over the substrate surface (e.g., after one or more other devices, such as a gate, have been formed), and an opening is etched in the oxide over a doped region in the substrate. Amorphous polysilicon is deposited in the opening, recrystallized and doped (e.g., by ion implant) to form a first thyristor base region that is adjacent to the doped substrate region, which forms a first emitter region for the thyristor. The polarity of the first thyristor base region is opposite to the polarity of the doped substrate region, with the first base region and the first emitter region forming an end portion (e.g., anode or cathode) of the vertical thin capacitively-coupled thyristor. A second base region is formed on the first base region having a polarity that is opposite to the polarity of the first base region. A second emitter region having a polarity that is opposite to the polarity of the first emitter region is formed on the second base region, with the second emitter and second base regions forming a second end portion (e.g., anode or cathode) of the thin capacitively-coupled thyristor. A portion of the oxide adjacent to the thin capacitively-coupled thyristor is removed and a thin capacitively coupled gate is formed in place of the oxide, adjacent one of the base regions and capacitively coupled to the base region.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.